1. Field of the Invention
The present invention relates generally to a semiconductor memory cell, and more particularly to a method of controlling threshold voltages of a NROM cell for multiple level cell (MLC) operation.
2. Description of the Related Art
Nitride Read Only Memory (NROM) cells are currently widely used in semiconductor industry. FIG. 1 illustrates a cross-sectional view of a conventional NROM cell with two bits storage capability. The NROM cell 100 includes a substrate 110 with doped source 112 and drain 114. A silicon nitride layer 116 is sandwiched between two silicon oxide layers 118 and 120 disposed over the substrate 110. A gate conductor 122 is disposed over the silicon oxide layer 120, and a channel 115 is formed under the silicon oxide layer 118 between drain 114 and source 112.
A NROM cell can be electrically programmed, read, and erased. The programming of the NROM cell 100 generates hot electrons in the channel 1115. A fraction of these hot electrons gain enough energy to surmount the barrier of the silicon oxide layer 118 and become trapped on the silicon nitride layer 116. The trapped charge will move to the region in the layer 116 near drain 114. Since the silicon nitride layer 116 is non-conductive, the NROM cell 100 can be programmed to have hot charges gathered at both ends of the layer 116: the right end near drain 114 with a stored charge 124 and the left end near source 112 with a stored charge 126.
When a NROM cell is read, the presence or absence of stored charge is determined by sensing the change in its threshold voltages. If a NROM cell is charged or programmed, its threshold voltage increases. The presence of stored charge is interpreted as the logical information signal “0”; the absence of stored charge is interpreted as the logical information signal “1”. As shown in FIG. 1, the NROM cell 100 has stored charges on both sides; therefore, the logical information signals for both bits of the NROM cell 100 are “0” and “0”.
A NROM cell capable of multiple levels of charges is said to have multiple level cell (MLC) operation capability. Different levels of charge results in different threshold voltages. The more the charge for a NROM cell, the higher its threshold voltage. The use of NROM cells with MLC operation capability leads to reduce the volume occupied by memory cells and produce dense semiconductor structures.
Conventional symmetrical programming and reading provides a method of a one-sided programming, reading, and erasing for a NROM cell. However, in order to achieve multiple threshold voltages, this method needs multiple program conditions.
U.S. Pat. No. 6,011,725 to Eitan discloses a method of asymmetrical programming, reading and erasing for a NROM cell with two bits storage capability. This invention suffers from the drawback that the void of interaction between the two bits of a NROM cell, due to the reverse read method, limits the threshold voltage operation window.
U.S. Pat. No. 6,487,114 B2 to Jong et al. discloses a method of simultaneously reading two bits of information for a NROM cell. Unfortunately, this method can read only up to four memory states for a two-bit NROM cell.
In view of the foregoing, there is a need for a method of controlling the threshold voltage of a NROM cell for MLC operation so that fewer programming conditions are needed to form multiple memory states.